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1 ? 2001 integrated device technology, inc. dsc-5713/4 time slot interchange digital switch 2,048 x 2,048 idt7290820 the idt logo is a registered trademark of integrated device technology, inc.

rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 ode f0i v cc cs ds/ rd r/ w / wr a0-a7 gnd cco dta d8-d15/ ad0-ad7 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 tx0 tx1 tx2 tx3 tx4 tx5 tx6 tx7 tx8 tx9 tx10 tx11 tx12 tx13 tx14 tx15 as/ ale im clk fe/ hclk wfps tdi tms tck tdo trst reset ic 5713 drw01 receive serial data streams output mux loopback test port data memory internal registers microprocessor interface timing unit connection memory transmit serial data streams ? 2,048 x 2,048 channel non-blocking switching at 8.192 mb/s ? per-channel variable or constant throughput delay ? automatic identification of st-bus ? /gci interfaces ? accept streams of 2.048 mb/s, 4.096 mb/s or 8.192 mb/s ? automatic frame offset delay measurement ? per-stream frame delay offset programming ? per-channel high impedance output control ? per-channel processor mode ? control interface compatible to intel/motorola cpus ? connection memory block programming ? ieee-1149.1 (jtag) test port ? available in 84-pin plastic leaded chip carrier (plcc), 100-pin ball grid array (bga), 100-pin plastic quad flatpack (pqfp) and 100-pin thin quad flatpack (tqfp) ? operating temperature range -40 c to +85 c ? 5v power supply
the idt7290820 is a non-blocking digital switch that has a capacity of 2,048 x 2,048 channels at a serial bit rate of 8.192 mb/s, 1,024 x 1,024 channels at 4.096 mb/s and 512 x 512 channels at 2.048 mb/s. some of the main features are: programmable stream and channel control, processor mode, input offset delay and high-impedance output control. per-stream input delay control is provided for managing large multi-chip switches that transport both voice channel and concatenated data channels. in addition, input streams can be individually calibrated for input frame offset.
2 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048

12 13 14 15 16 17 18 19 20 4 3 2 1 83 82 81 39 40 41 42 43 44 45 index 5713 drw03 7 6 5 80 79 78 77 76 75 8 11 10 9 46 47 48 49 50 51 52 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 73 72 71 70 69 68 67 66 65 55 54 21 22 23 24 25 26 27 28 29 30 31 32 53 74 84 cco dta d15 d14 d13 d12 d11 d10 d9 d8 gnd vcc ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 gnd rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 f0i fe/hclk gnd clk vcc tms tdi tdo tck trst ic reset wfps a0 a1 a2 a3 a4 a5 a6 a7 ds/ rd r/ w / rw cs as/ale im gnd tx15 tx14 tx13 tx12 tx11 tx10 tx9 tx8 vcc gnd tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 ode gnd a b c d e f g h j k rx0 rx2 rx7 rx10 rx5 rx11 rx13 rx14 foi tms tx13 rx1 rx8 rx9 rx4 rx12 rx15 fe/ hclk tdi tdo tx11 tx14 rx6 vcc rx3 vcc clk tck trst ic tx10 tx12 vcc d11 d14 cco d13 ode tx0 d10 dta tx2 tx3 vcc vcc tx5 tx4 gnd gnd gnd gnd gnd tx6 tx7 gnd tx9 tx8 10 9 8 7 6 5 4 3 2 1 a1 ball pad corner d9 d12 d8 ad5 ad3 ad0 as/ale dnc gnd vcc cs a7 a5 vcc gnd gnd vcc a4 a3 a6 d15 ad7 ad6 ad2 im ds/rd tx1 vcc ad4 ad1 r/ w / rw vcc gnd gnd vcc a1 a2 tx15 gnd vcc reset a0 wfps 5713 drw02 bga: 1mm pitch, 11mm x 11mm (bc100-1, order code: bc) top view plcc: 0.05in. pitch, 1.15in. x 1.15in. (pl84-1, order code: j) top view notes: 1. dnc - do not connect 2. ic - internal connection, tie to ground for normal operation.
3 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 index 5713 drw04 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 76 77 78 79 90 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 dnc dnc dnc dnc rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 f0i fe/hclk gnd clk vcc cco dta d15 d14 d13 d12 d11 d10 d9 d8 gnd vcc ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 gnd dnc dnc dnc dnc dnc dnc dnc dnc tms tdi tdo tck trst ic reset wfps a0 a1 a2 a3 a4 a5 a6 a7 ds/ rd r/ w / rw cs as/ale im gnd tx15 tx14 tx13 tx12 tx11 tx10 tx9 tx8 vcc gnd tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 ode gnd dnc dnc dnc dnc

!" index 5713 drw05 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rx0 rx1 rx2 rx3 rx4 rx5 rx6 rx7 rx8 rx9 rx10 rx11 rx12 rx13 rx14 rx15 foi fe/hclk clk dta d15 d14 d13 d12 d11 d10 d9 d8 gnd vcc ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 gnd dnc dnc dnc dnc vcc tms tdi tdo tck trst ic reset wfps a0 a1 a2 a3 a4 a5 a6 a7 ds/ rd r/ w / wr cs as/ale im dnc dnc dnc dnc dnc dnc dnc dnc gnd tx15 tx14 tx13 tx12 tx11 tx10 tx9 tx8 vcc gnd tx7 tx6 tx5 tx4 tx3 tx2 tx1 tx0 ode gnd cco dnc dnc dnc dnc gnd 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 100 99 pqfp: 0.65mm pitch, 14mm x 20mm (pq100-2, order code: pqf) top view tqfp: 0.50mm pitch, 14mm x 14mm (pn100-1, order code: pf) top view
4 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048

symbol name i/o description gnd ground. ground rail. vcc vcc +5.0 volt power supply. tx0-15 (1) tx output 0 to 15 o serial data output stream. these streams may have data rates of 2.048, 4.096 or 8.192 mb/s, depending up on (three-state outputs) the value programmed at bits dr0-1 in the ims register. rx0-15 (1) rx input 0 to 15 i serial data input stream. these streams may have data rates of 2.048, 4.096 or 8.192 mb/s, depending upon the value programmed at bits dr0-1 in the ims register. f0i (1) frame pulse i when the wfps pin is low, this input accepts and automatically identifies frame synchronization signals formatte d according to st-bus ? and gci specifications. when the wfps pin is high, this pin accepts a negative frame pulse which conforms to wfps formats. fe/hclk (1) frame evaluation/ i when the wfps pin is low, this pin is the frame measurement input. when the wfps pin is high, the hclk hclk clock (4.096 mhz clock) is required for frame alignment in the wide frame pulse (wfp) mode. clk (1) clock i serial clock for shifting data in/out on the serial streams (rx/tx 0-15). depending upon the value programmed at bits dr0-1 in the ims register, this input accepts a 4.096, 8.192 or 16.384 mhz clock. tms test mode select i jtag signal that controls the state transitions of the tap controller. this pin is pulled high by an int ernal pull- up when not driven. tdi test serial data in i jtag serial test instructions and data are shifted in on this pin. this pin is pulled high by an inte rnal pull-up when not driven. tdo test serial data out o jtag serial data is output on this pin on the falling edge of tck. this pin is held in high-impedanc e state when jtag scan is not enabled. tck (1) test clock i provides the clock to the jtag test logic. this pin is pulled high by an internal pull-up when not driven. trst test reset i asynchronously initializes the jtag tap controller by putting it in the test-logic-reset state. this pin is pull ed by an internal pull-up when not driven. this pin should be pulsed low on power-up, or held low, to ensure that the idt7290820 is in the normal functional mode. ic (1) internal connection i connect to gnd for normal operation. this pin must be low for the idt7290820 to function normally and to comply with ieee 1114 (jtag) boundary scan requirements. reset (1) device reset i this input (active low) puts the idt7290820 in its reset state that clears the device internal counters, regist ers (schmitt trigger input) and brings tx0-15 and microport data outputs to a high-impedance state. the time constant for a power up reset circuit must be a minimum of five times the rise time of the power supply. in normal operation, the reset pin must be held low for a minimum of 100ns to reset the device. wfps (1) wide frame i when 1, enables the wide frame pulse (wfp) frame alignment interface. when 0, the device operates in pulse select st-bus ? /gci mode. a0-7 (1) address 0-7 i when non-multiplexed cpu bus operation is selected, these lines provide the a0-a7 address lines to the internal memories. ds/ rd (1) data strobe/read i for motorola multiplexed bus operation, this input is ds. this active high ds input works in conjunction wi th cs to enable the read and write operations. for motorola non-multiplexed cpu bus operation, this input is ds. this active low input works in conjunction with cs to enable the read and write operations. for intel multiplexed bus operation, this input is rd . this active low input sets the data bus lines (ad0-7, d8-15) as outputs. r/ w / wr (1) read/write / write i in the cases of motorola non-multiplexed and multiplexed bus operations, this input is r/ w . this input controls the direction of the data bus lines (ad0-7, d8-15) during a microprocessor access. for intel multiplexed bus operation, this input is wr . this active low input is used with rd to control the data bus (ad0-7) lines as inputs. cs (1) chip select i active low input used by a microprocessor to activate the microprocessor port of idt7290820. as/ale (1) address strobe or i this input is used if multiplexed bus operation is selected via the im input pin. for motorola non-multipl exed latch enable bus operation, connect this pin to ground. this pin is pulled low by an internal pull-down when not driven. im (1) cpu interface mode i when im is high, the microprocessor port is in the multiplexed mode. when im is low, the microprocessor port is in non-multiplexed mode. this pin is pulled low by an internal pull-down when not driven. ad0-7 (1) address/data bus 0 to 7 i/o these pins are the eight least significant data bits of the microprocessor port. in multiplexed m ode, these pins are also the input address bits of the microprocessor port. note: 1. these pins are 5v tolerant.
5 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 d8-15 (1) data bus 8-15 i/o these pins are the eight most significant data bits of the microprocessor port. dta (1) data transfer o this active low output signal indicates that a data bus transfer is complete. when the bus cycle ends, this pi n acknowledgment drives high and then goes high-impedance, allowing for faster bus cycles with a weaker pull-up resistor. a pull-up resistor is required to hold a high level when the pin is in high-impedance. cco (1) control output o this is a 4.096, 8.192 or 16.384 mb/s output containing 512, 1,024 or 2.048 bits per frame respectively. the level of each bit is determined by the cco bit in the connection memory. see external drive control section. ode (1) output drive enable i this is the output enable control for the tx0 to tx15 serial outputs. when ode input is low and the osb bit of the ims register is low, tx0-15 are in a high-impedance state. if this input is high, the tx0-15 output drivers are enabled. however, each channel may still be put into a high-impedance state by using the per channel control bit in the connection memory.

" symbol name i/o description note: 1. these pins are 5v tolerant.
6 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048

the idt7290820 is capable of switching up to 2,048 x 2,048, 64 kbit/s pcm or n x 64 kbit/s channel data. the device maintains frame integrity in data applications and minimum throughput delay for voice applications on a per channel basis. the serial input streams of the idt7290820 can have a bit rate of 2.048, 4.096 or 8.192 mb/s and are arranged in 125 s wide frames, which contain 32, 64 or 128 channels respectively. the data rates on input and output streams are identical. in processor mode, the microprocessor can access input and output time- slots on a per channel basis allowing for transfer of control and status information. the idt7290820 automatically identifies the polarity of the frame synchroniza- tion input signal and configures the serial streams to either st-bus ? or gci formats. with the variety of different microprocessor interfaces, idt7290820 has provided an input mode pin (im) to help integrate the device into different microprocessor based environments: non-multiplexed or multiplexed. these interfaces provide compatibility with multiplexed and motorola non-multiplexed buses. the device can also resolve different control signals eliminating the use of glue logic necessary to convert the signals (r/ w / wr , ds/ rd , as/ale). the frame offset calibration function allows users to measure the frame offset delay using a frame evaluation pin (fe). the input offset delay can be programmed for individual streams using internal frame input offset registers, see table 11. the internal loopback allows the tx output data to be looped around to the rx inputs for diagnostic purposes. a functional block diagram of the idt7290820 is shown in figure 1. data and connection memory the received serial data is converted to parallel format by internal serial- to-parallel converters and stored sequentially in the data memory. the 8khz input frame pulse ( f0i ) is used to generate channel and frame boundaries of the input serial data. depending on the interface mode select (ims) register, the usable data memory may be as large as 2,048 bytes. data to be output on the serial streams (tx0-15) may come from either the data memory or connection memory. for data output from data memory (connection mode), addresses in the connection memory are used. for data to be output from connection memory, the connection memory control bits must set the particular tx output in processor mode. one time-slot before the data is to be output, data from either connection memory or data memory is read internally. this allows enough time for memory access and parallel-to-serial conversion. connection and processor modes in the connection mode, the addresses of the input source data for all output channels are stored in the connection memory. the connection memory is mapped in such a way that each location corresponds to an output channel on the output streams. for details on the use of the source address data (cab and sab bits), see table 13 and table 14. once the source address bits are programmed by the microprocessor, the contents of the data memory at the selected address are transferred to the parallel-to-serial converters and then onto a tx output stream. by having the each location in the connection memory specify an input channel, multiple outputs can specify the same input address. this can be a powerful tool used for broadcasting data. in processor mode, the microprocessor writes data to the connection memory. each location in the connection memory corresponds to a particular output stream and channel number and is transferred directly to the parallel-to- serial converter one time-slot before it is to be output. this data will be output on the tx streams in every frame until the data is changed by the microprocessor. as the idt7290820 can be used in a wide variety of applications, the device also has memory locations to control the outputs based on operating mode. specifically, the idt7290820 provides five per-channel control bits for the following functions: processor or connection mode, constant or variable delay, enables/three-state the tx output drivers and enables/disable the loopback function. in addition, one of these bits allows the user to control the cco output. if an output channel is set to a high-impedance state through the connection memory, the tx output will be in a high-impedance state for the duration of that channel. in addition to the per-channel control, all channels on the st-bus ? outputs can be placed in a high impedance state by either pulling the ode input pin low or programming the output stand-by (osb) bit in the interface mode selection register. this action overrides the per-channel programming in the connection memory bits. the connection memory data can be accessed via the microprocessor interface. the addressing of the devices internal registers, data and connection memories is performed through the address input pins and the memory select (ms) bit of the control register. for details on device addressing, see software control and control register bits description (table 4, 6 and 7). serial data interface timing the master clock frequency must always be twice the data rate. for serial data rates of 2.048, 4.096 or 8.192 mb/s, the master clock (clk) must be either at 4.096, 8.192 or 16.384 mhz respectively. the input and output stream data rates will always be identical. the idt7290820 provides two different interface timing modes st-bus ? / gci and wfp (wide frame pulse). if the wfps pin is high, the idt7290820 is in the wide frame pulse (wfp) frame alignment mode. in st-bus ? /gci mode, the input 8 khz frame pulse can be in either st-bus ? or gci format. the idt7290820 automatically detects the presence of an input frame pulse and identifies it as either st-bus ? or gci. in st-bus ? format, every second falling edge of the master clock marks a bit boundary and the data is clocked in on the rising edge of clk, three quarters of the way into the bit cell, see figure 7. in gci format, every second rising edge of the master clock marks the bit boundary and data is clocked in on the falling edge of clk at three quarters of the way into the bit cell, see figure 8. wide frame pulse (wfp) frame alignment timing when the device is in wfp frame alignment mode, the clk input must be at 16.384 mhz, the fe/hclk input is 4.096 mhz and the 8 khz frame pulse is in st-bus ? format. the timing relationship between clk, hclk and the frame pulse is shown in figure 9. when wfps pin is high, the frame alignment evaluation feature is disabled. however, the frame input offset registers may still be programmed to compensate for the varying frame delays on the serial input streams.
7 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ? # $

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the idt7290820 can operate at different speeds. to configure the maximum non-blocking switching data rate, the two dr bits in the ims register are used. following are the possible configurations: 2.048 mb/s serial links (dr0=0, dr1=0) when the 2.048 mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 32, 64 kbit/s channels each. this mode requires a clk of 4.096 mhz and allows a maximum non-blocking capacity of 512 x 512 channels. 4.096 mb/s serial links (dr0=1, dr1=0) when the 4.096 mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 64, 64 kbit/s channels each. this mode requires a clk of 8.192 mhz and allows a maximum non-blocking capacity of 1,024 x 1,024 channels. 8.192 mb/s serial links (dr0=0, dr1=1) when the 8.192 mb/s data rate is selected, the device is configured with 16-input/16-output data streams each having 128, 64 kbit/s channels each. this mode requires a clk of 16.384 mhz and allows a maximum non-blocking capacity of 2,048 x 2,048 channels. table 1 summarizes the switching configurations and the relationship between different serial data rates and the master clock frequencies. input frame offset selection input frame offset selection allows the channel alignment of individual input streams to be offset with respect to the output stream channel alignment (i.e. f0i ). although all input data comes in at the same speed, delays can be caused by variable path serial backplanes and variable path lengths which may be implemented in large centralized and distributed switching systems. because data is often delayed, this feature is useful in compensating for the skew between clocks. each input stream can have its own delay offset value by programming the frame input offset registers (for). the maximum allowable skew is +4.5 master clock (clk) periods forward with resolution of 1/2 clock period. the output frame offset cannot be offset or adjusted. see figure 5, table 11 and 12 for delay offset programming. serial input frame alignment evaluation the idt7290820 provides the frame evaluation (fe) input to determine different data input delays with respect to the frame pulse f0i . a measurement cycle is started by setting the start frame evaluation (sfe) bit low for at least one frame. when the sfe bit in the ims register is changed from low to high, the evaluation starts. two frames later, the complete frame evaluation (cfe) bit of the frame alignment register (far) changes from low to high to signal that a valid offset measurement is ready to be read from bits 0 to 11 of the far register. the sfe bit must be set to zero before a new measurement cycle started. in st-bus ? mode, the falling edge of the frame measurement signal (fe) is evaluated against the falling edge of the st-bus ? frame pulse. in gci mode, the rising edge of fe is evaluated against the rising edge of the gci frame pulse. see table 10 & figure 4 for the description of the frame alignment register. this feature is not available when the wfp frame alignment mode is enabled (i.e., when the wfps pin is connected to vcc). memory block programming the idt7290820 provides users with the capability of initializing the entire connection memory block in two frames. to set bits 11 to 15 of every connection memory location, first program the desired pattern in bits 5 to 9 of the ims register. the block programming mode is enabled by setting the memory block program (mbp) bit of the control register high. when the block programming enable (bpe) bit of the ims register is set to high, the block programming data will be loaded into the bits 11 to 15 of every connection memory location. the other connection memory bits (bit 0 to bit 10) are loaded with zeros. when the memory block programming is complete, the device resets the bpe bit to zero. loopback control the loopback control (lpbk) bit of each connection memory location allows the tx output data to be looped backed internally to the rx input for diagnostic purposes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., data from tx n channel m routes to the rx n channel m internally); if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of frame delay offset registers must be set to zero. $$$ %&' the switching of information from the input serial streams to the output serial streams results in a throughput delay. the device can be programmed to perform time-slot interchange functions with different throughput delay capabili- ties on the per-channel basis. for voice applications, variable throughput delay is best as it ensures minimum delay between input and output data. in wideband data applications, constant throughput delay is best as the frame integrity of the information is maintained through the switch. the delay through the device varies according to the type of throughput delay selected in the v /c bit of the connection memory. variable delay mode ( v /c bit = 0) in this mode, the delay is dependent only on the combination of source and destination channels and is independent of input and output streams. the minimum delay achievable in the idt7290820 is three time-slots. if the input channel data is switched to the same output channel (channel n, frame p), it will be output in the following frame (channel n, frame p+1). the same is true if input channel n is switched to output channel n+1 or n+2. if the input channel n is switched to output channel n+3, n+4,..., the new output data will appear in the same frame. table 2 shows the possible delays for the idt7290820 in the variable delay mode. serial interface master clock required matrix channel data rate (mhz) capacity 2.048 mb/s 4.096 512 x 512 4.096 mb/s 8.192 1,024 x 1,024 8.192 mb/s 16.384 2,048 x 2,048
8 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 constant delay mode ( v /c bit = 1) in this mode, frame integrity is maintained in all switching configurations by making use of a multiple data memory buffer. input channel data is written into the data memory buffers during frame n will be read out during frame n+2. in the idt7290820, the minimum throughput delay achievable in the constant delay mode will be one frame. for example, in 2.048 mb/s mode, when input time-slot 31 is switched to output time-slot 0. the maximum delay of 94 time-slots of delay occurs when time-slot 0 in a frame is switched to time-slot 31 in the frame. see table 3.
the idt7290820 provides a parallel microprocessor interface for multi- plexed or non-multiplexed bus structures. this interface is compatible with motorola non-multiplexed and multiplexed buses. if the im pin is low a motorola non-multiplexed bus should be connected to the device. if the im pin is high, the device monitors the as/ale and ds/ rd to determine what mode the idt7290820 should operate in. if ds/ rd is low at the rising edge of as/ale, then the mode 1 multiplexed timing is selected. if ds/ rd is high at the rising edge of as/ale, then the mode 2 multiplexed bus timing is selected. for multiplexed operation, the required signals are the 8-bit data and address (ad0-ad7), 8-bit data (d8-d15), address strobe/address latch enable (as/ ale), data strobe/read (ds/ rd ), read/write /write (r/ w / wr ), chip select ( cs ) and data transfer acknowledge ( dta ). see figure 12 and figure 13 for multiplexed parallel microport timing. for the motorola non-multiplexed bus, the required signals are the 16-bit data bus (ad0-ad7, d8-d15), 8-bit address bus (a0-a7) and 4 control lines ( cs , ds, r/ w and dta ). see figure 14 and 15 for motorola non-multiplexed microport timing. the idt7290820 microport provides access to the internal registers, connection and data memories. all locations provide read/write access except for the data memory and the frame alignment register which are read only. memory mapping the address bus on the microprocessor interface selects the internal registers and memories of the idt7290820. if the a7 address input is low, then a6 through a0 are used to address the interface mode selection (ims), control (cr), frame alignment (far) and frame input offset (for) registers (table 4). if the a7 is high, then a6 through a0 are used to select 32, 64, or 128 locations corresponding to data rate of the st-bus ? . the address input lines and the stream address bits (sta) of the control register allow access to the entire data and connection memories. the control and ims registers together control all the major functions of the device, see figure 3. as explained in the serial data interface timing and switching configura- tions sections, after system power-up, the ims register should be programmed immediately to establish the desired switching configuration. the data in the control register consists of the memory block programming bit (mbp), the memory select bit (ms) and the stream address bits (sta). as explained in the memory block programming section, the mbp bit allows the entire connection memory block to be programmed. the memory select bit is used to designate the connection memory or the data memory. the stream address bits select internal memory subsections corresponding to input or output serial streams. the data in the ims register consists of block programming bits (bpd0- bpd4), block programming enable bit (bpe), output stand by bit (osb), start frame evaluation bit (sfe) and data rate selection bits (dr0-1). the block programming and the block programming enable bits allows users to program the entire connection memory (see memory block programming section). if the ode pin is low, the osb bit enables (if high) or disables (if low) all st-bus ? output drivers. if the ode pin is high, the contents of the osb bit is ignored and all tx output drivers are enabled. connection memory control the cco pin is a 4.096, 8.192 or 16.384 mb/s output, which carries 512, 1,024 or 2,048 bits, respectively. the contents of the cco bit of each connection memory location are output on the cco pin once every frame. the contents of the cco bits of the connection memory are transmitted sequentially on to the cco pin and are synchronous with the data rates on the other serial streams. the cco bit is output one channel before the corresponding channel on the serial streams. for example, in 2.048 mb/s mode (32 channels per frame), the contents of the cco bit in position 0 (tx0, ch0) of the connection memory is output on the first clock cycle of channel 31 through cco pin. the contents of the cco bit in position 32 (tx1, ch0) of the connection memory is output on the second clock cycle of channel 31 via cco pin. if the ode pin or the osb bit is high, the oe bit of each connection memory location controls the output drivers-enables (if high) or disables (if low). see table 5 for detail. the processor channel (pc) bit of the connection memory selects between processor mode and connection mode. if high, the contents of the connection memory are output on the tx streams. if low, the stream address bit (sab) and the channel address bit (cab) of the connection memory defines the source information (stream and channel) of the time-slot that will be switched to the output from data memory. the v /c (variable/constant delay) bit in each connection memory location allows the per-channel selection between variable and constant throughput delay modes. if the lpbk bit is high, the associated tx output channel data is internally looped back to the rx input channel (i.e., rx n channel m data comes from the tx n channel m). if the lpbk bit is low, the loopback feature is disabled. for proper per-channel loopback operation, the contents of the frame delay offset registers must be set to zero.
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$ %&' after power up, the state of the connection memory is unknown. as such, the outputs should be put in high impedance by holding the ode low. while the ode is low, the microprocessor can initialize the device, program the active paths, and disable unused outputs by programming the oe bit in connection memory. once the device is configured, the ode pin (or osb bit depending on initialization) can be switched.
9 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 connection memory data memory 1 0 control register cr b 7 5713 drw06 10000000 the control register is only accessed when a7-a0 are all zeroed. when a7 =1, up to 128 bytes are randomly accessa- ble via a0-a6 at any one instant. of which stream these bytes (channels) are accessed is determined by the state of cr b 3 -cr b 0. cr b 6cr b 5cr b 4cr b 2cr b 1cr b 0 cr b 4 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7 stream cr b 2cr b 1cr b 0 0 0 0 0 0 0 0 0 cr b 3 cr b 3 8 9 10 11 12 13 14 15 000 001 010 011 100 101 110 111 1 1 1 1 1 1 1 1 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 127 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 10000001 10000010 11111111 external address bits a7-a0 figure 3. addressing internal memories
10 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ) ?

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? * $$* delay for variable throughput delay mode input rate (m ? output channel number) (n ? input channel number) m < n m = n, n+1, n+2 m > n+2 2.048 mb/s 32 ? (n-m) time-slots m-n + 32 time slots m-n time-slots 4.096 mb/s 64 ? (n-m) time-slots m-n + 64 time-slots m-n time slots 8.192 mb/s 128 ? (n-m) time-slots m-n + 128 time-slots m-n time-slots delay for constant throughput delay mode input rate (m ? output channel number) (n ? input channel number) 2.048 mb/s 32 + (32 ? n) + m time-slots 4.096 mb/s 64 + (64 ? n) + m time-slots 8.192 mb/s 128 + (128 ? n) + m time-slots a7 (1) a6 a5 a4 a3 a2 a1 a0 location 00000000 control register, cr 00000001 interface mode selection register, ims 00000010 frame alignment register, far 00000011 frame input offset register 0, for0 00000100 frame input offset register 1, for1 00000101 frame input offset register 2, for2 00000110 frame input offset register 3, for3 10000000ch0 10000001ch1 100...... 10011110 ch30 10011111 ch31 (note 2) 10100000 ch32 10100001 ch33 101...... 10111110 ch62 10111111 ch63 (note 3) 11000000 ch64 11000001 ch65 110...... 11111110 ch126 11111111 ch127 (note 4) notes: 1. bit a7 must be high for access to data and connection memory positions. bit a7 must be low for access to registers. 2. channels 0 to 31 are used when serial interface is at 2.048 mb/s mode 3. channels 0 to 63 are used when serial interface is at 4.096 mb/s mode. 4. channels 0 to 127 are used when serial interface is at 8.192 mb/s mode.
11 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 , ?
" % ? *

- ? $ $

oe bit in connection ode pin osb bit in ims tx output driver memory register status 0 don?t care don?t care per channel high-impedance 1 0 0 high-impedance 1 0 1 enable 1 1 1 enable 1 1 0 enable read/write address: 00 h , reset value: 0000 h . 1514131211109876543210 0000000000mbpms sta3 sta2 sta1 sta0 bit name description 15-6 unused must be zero for normal operation. 5 mbp when 1, the connection memory block programming feature is ready for the programming of connection (memory block program) memory high bits, bit 11 to bit 15. when 0, this feature is disabled. 4 ms when 0, connection memory is selected for read or write operations. when 1, the data memory is selected (memory select) for read operations and connection memory is selected for write operations. (no microprocessor write operation is allowed for the data memory). 3-0 sta3-0 the binary value expressed by these bits refers to the input or output data stream, which corresponds (stream address bits) to the subsection of memory made accessible for subsequent operations. (sta3 = msb, sta0 = lsb) input/output valid address lines data rate 2.048 mb/s a4, a3, a2, a1, a0 4.096 mb/s a5, a4, a3, a2, a1, a0 8.192 mb/s a6, a5, a4, a3, a2, a1, a0
12 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ' ?

" & ?
,
.," dr1 dr0 data rate selected master clock required 0 0 2.048 mb/s 4.096 mhz 0 1 4.096 mb/s 8.192 mhz 1 0 8.192 mb/s 16.384 mhz 1 1 reserved reserved read/write address: 01 h , reset value: 0000 h . bit name description 15-10 unused must be zero for normal operation. 9-5 bpd4-0 these bits carry the value to be loaded into the connection memory block whenever the memory block (block programming data) programming feature is activated. after the mbp bit in the control register is set to 1 and the bpe bit is set to 1, the contents of the bits bpd4-0 are loaded into bit 15 and 11 of the connection memory. bit 10 to bit 0 of the connection memory are set to 0. 4 bpe a zero to one transition of this bit enables the memory block programming function. the bpe and (begin block programming bpd4-0 bits in the ims register have to be defined in the same write operation. once the bpe bit is set enable) high, the device requires two frames to complete the block programming. after the programming function has finished, the bpe bit returns to zero to indicate the operation is completed. when the bpe = 1, the bpe or mbp can be set to 0 to ensure proper operation. when bpe = 1, the other bit in the ims register must not be changed for two frames to ensure proper operation. 3 osb when ode = 0 and osb = 0, the output drivers of tx0 to tx15 are in high impedance mode. when (output stand by) ode= 0 and osb = 1, the output driver of tx0 to tx15 function normally. when ode = 1, tx0 to tx15 output drivers function normally. 2 sfe a zero to one transition in this bit starts the frame evaluation procedure. when the cfe bit in the far (start frame evaluation) register changes from zero to one, the evaluation procedure stops. to start another fame evaluation cycle, set this bit to zero for at least one frame. 1-0 dr0-1 input/output data rate selection. see table 9 for detailed programming. (data rate select) 1514131211109876543210 000000 bpd4 bpd3 bpd2 bpd1 bpd0 bpe osb sfe dr1 dr0
13 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 0123 456 78 9101112131415 16 st-bus ? frame clk offset value fe input 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 gci frame clk offset value fe input (fd[10:0] = 06 h ) (fd11 = 0, sample at clk low phase) (fd[10:0] = 09 h ) (fd11 = 1, sample at clk high phase) 5713 drw07 ?

" figure 4. example for frame alignment measurement bit name description 15-13 unused must be zero for normal operation. 12 cfe when cfe = 1, the frame evaluation is completed and bits fd10 to fd0 bits contains a valid frame alignment (complete frame evaluation) offset. this bit is reset to zero, when sfe bit in the ims register is changed from 1 to 0. 11 fd11 the falling edge of fe (or rising edge for gci mode) is sampled during the clk-high phase (fd11 = 1) (frame delay bit 11) or during the clk-low phase (fd11 = 0). this bit allows the measurement resolution to ? clk cycle. 10-0 fd10-0 the binary value expressed in these bits refers to the measured input offset value. these bits are rest to (frame delay bits) zero when the sfe bit of the ims register changes from 1 to 0. (fd10 ? msb, fd0 ? lsb) read/write address: 02 h , reset value: 0000 h . 1514131211109876543210 0 0 0 cfe fd11 fd10 fd9 fd8 fd7 fd6 fd5 fd4 fd3 fd2 fd1 fd0
14 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ?
" name (1) description ofn2, ofn1, ofn0 these three bits define how long the serial interface receiver takes to recognize and store bit 0 from the rx i nput pin: i.e., to (offset bits 2, 1 & 0) start a new frame. the input frame offset can be selected to +4.5 clock periods from the point where the external frame pulse input signal is applied to the f0i input of the device. see figure 5. dlen (data latch edge) st-bus ? mode: dlen = 0, if clock rising edge is at the ? point of the bit cell. dlen = 1, if when clock falling edge is at the ? of the bit cell. gci mode: dlen = 0, if clock falling edge is at the ? point of the bit cell. dlen = 1, if when clock rising edge is at the ? of the bit cell. read/write address: 03 h for for0 register, 04 h for for1 register, 05 h for for2 register, 06 h for for3 register, reset value: 0000 h for all for registers. 1514131211109876543210 of32 of31 of30 dle3 of22 of21 of20 dle2 of12 of11 of10 dle1 of02 of01 of00 dle0 for0 register 1514131211109876543210 of72 of71 of70 dle7 of62 of61 of60 dle6 of52 of51 of50 dle5 of42 of41 of40 dle4 for1 register 1514131211109876543210 of112 of111 of110 dle11 of102 of101 of100 dle10 of92 of91 of90 dle9 of82 of81 of80 dle8 for2 register 1514131211109876543210 of152 of151 of150 dle15 of142 of141 of140 dle14 of132 of131 of130 dle13 of122 of121 of120 dle12 for3 register note: 1. n denotes an input stream number from 0 to 15.
15 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 st-bus ? f0i rx stream 5713 drw08 bit 7 bit 7 clk bit 7 bit 7 denotes the 3/4 point of the bit cell offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 offset = 1, dle = 1 gci f0i bit 0 bit 0 clk bit 0 bit 0 denotes the 3/4 point of the bit cell offset = 0, dle = 0 offset = 1, dle = 0 offset = 0, dle = 1 offset = 1, dle = 1 rx stream rx stream rx stream rx stream rx stream rx stream rx stream ? / / /"0 / 1" figure 5. examples for input offset delay timing measurement result from corresponding input stream frame delay bits offset bits offset fd11 fd2 fd1 fd0 ofn2 ofn1 ofn0 dlen no clock period shift (default) 1000000 0 + 0.5 clock period shift 0000000 1 + 1.0 clock period shift 1001001 0 + 1.5 clock period shift 0001001 1 + 2.0 clock period shift 1010010 0 + 2.5 clock period shift 0010010 1 + 3.0 clock period shift 1011011 0 + 3.5 clock period shift 0011011 1 + 4.0 clock period shift 1100100 0 + 4.5 clock period shift 0100100 1
16 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ) ?

+ ?

note: 1. if bit 13 (pc) of the corresponding connection memory location is 1 (device in processor mode), then these entire 8 bits (sab 0, cab6 - cab0) are output on the output channel and stream associated with this location. bit name description 15 lpbk when 1, the rx n channel m data comes from the tx n channel m. for proper per channel loopback (per channel loopback) operations, set the delay offset register bits ofn[2:0] to zero for the streams which are in the loopback mode. 14 v /c this bit is used to select between the variable (low) and constant delay (high) mode on a (variable/constant per-channel basis. throughput delay) 13 pc when 1, the contents of the connection memory are output on the corresponding output channel and stream. (processor channel) only the lower byte (bit 7 ? bit 0) will be output to the tx output pins. when 0, the contents of the connec tion memory are the data memory address of the switched input channel and stream. 12 cco this bit is output on the cco pin one channel early. the cco bit for stream 0 is output first. (control channel output) 11 oe this bit enables the tx output drivers on a per-channel basis. when 1, the output driver functions (output enable) normally. when 0, the output driver is in a high-impedance state. 10-8,7 (1) sab3-0 the binary value is the number of the data stream for the source of the connection. (source stream address bits) 6-0 (1) cab6-0 the binary value is the number of the channel for the source of the connection. (source channel address bits) 1514131211109876543210 lpbk v /c pc cco oe sab3 sab2 sab1 sab0 cab6 cab5 cab4 cab3 cab2 cab1 cab0 data rate cab bits used to determine the source channel of the connection 2.048 mb/s cab4 to cab0 (32 channel/input stream) 4.096 mb/s cab5 to cab0 (64 channel/input stream) 8.192 mb/s cab6 to cab0 (128 channel/input stream)
17 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 the idt7290820 jtag interface conforms to the boundary-scan standard ieee-1149.1. this standard specifies a design-for-testability technique called boundary-scan test (bst). the operation of the boundary-scan circuitry is controlled by an external test access port (tap) controller. test access port (tap) the test access port (tap) provides access to the test functions of the idt7290820. it consists of three input pins and one output pin. test clock input (tck) tck provides the clock for the test logic. the tck does not interfere with any on-chip clock and thus remain independent. the tck permits shifting of test data into or out of the boundary-scan register cells concurrently with the operation of the device and without interfering with the on-chip logic. test mode select input (tms) the logic signals received at the tms input are interpreted by the tap controller to control the test operations. the tms signals are sampled at the rising edge of the tck pulse. this pin is internally pulled to vcc when it is not driven from an external source. test data input (tdi) serial input data applied to this port is fed either into the instruction register or into a test data register, depending on the sequence previously applied to the tms input. both registers are described in a subsequent section. the received input data is sampled at the rising edge of tck pulses. this pin is internally pulled to vcc when it is not driven from an external source. test data output (tdo) depending on the sequence previously applied to the tms input, the contents of either the instruction register or data register are serially shifted out towards the tdo. the data out of the tdo is clocked on the falling edge of the tck pulses. when no data is shifted through the boundary scan cells, the tdo driver is set to a high impedance state. test reset ( trst ) reset the jtag scan structure. this pin is internally pulled to vcc. instruction register in accordance with the ieee 1149.1 standard, the idt7290820 uses public instructions. the idt7290820 jtag interface contains a two-bit instruction register. instructions are serially loaded into the instruction register from the tdi when the tap controller is in its shifted-ir state. subsequently, the instructions are decoded to achieve two basic functions: to select the test data register that may operate while the instruction is current, and to define the serial test data register path, which is used to shift data between tdi and tdo during data register scanning. see table below for instruction decoding. value instruction function 11 bypass select bypass register 10 sample/period select boundry scan register 01 sample/period select boundry scan register 00 extest select boundry scan register test data register as specified in ieee 1149.1, the idt7290820 jtag interface contains two test data registers: the boundary-scan register the boundary-scan register consists of a series of boundary-scan cells arranged to form a scan path around the boundary of the idt7290820 core logic. the bypass register the bypass register is a single stage shift register that provides a one-bit path from tdi to its tdo. the idt7290820 boundary scan register contains 118 bits. bit 0 in table 15 boundary scan register is the first bit clocked out. all three-state enable bits are active high. jtag instruction register decoding
18 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 - ?

boundary scan bit 0 to bit 117 device pin three-state output input control scan cell scan cell a4 76 a3 77 a2 78 a1 79 a0 80 wfps 81 reset 82 clk 83 fe/hclk 84 f0i 85 rx15 86 rx14 87 rx13 88 rx12 89 rx11 90 rx10 91 rx9 92 rx8 93 rx7 94 rx6 95 rx5 96 rx4 97 rx3 98 rx2 99 rx1 100 rx0 101 tx15 102 103 tx14 104 105 tx13 106 107 tx12 108 109 tx11 110 111 tx10 112 113 tx9 114 115 tx8 116 117 boundary scan bit 0 to bit 117 device pin three-state output input control scan cell scan cell tx7 0 1 tx6 2 3 tx5 4 5 tx4 6 7 tx3 8 9 tx2 10 11 tx1 12 13 tx0 14 15 ode 16 cco 17 18 dta 19 d15 20 21 22 d14 23 24 25 d13 26 27 28 d12 29 30 31 d11 32 33 34 d10 35 36 37 d9 38 39 40 d8 41 42 43 ad7 44 45 46 ad6 47 48 49 ad5 50 51 52 ad4 53 54 55 ad3 56 57 58 ad2 59 60 61 ad1 62 63 64 ad0 65 66 67 im 68 ad/ale 69 cs 70 r/ w / wr 71 ds/ rd 72 a7 73 a6 74 a5 75
19 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048

$ note: 1. voltages are with respect to ground unless other wise stated. note: 1. outputs unloaded. 2. for tdi, tms, tck, trst, as/ale and im pins, the maximum leakage current is 50 a. test point output pin c l gnd s 1 r l vcc gnd 5713 drw09 s 2 symbol parameter min. typ. max. units v cc positive supply 4.75 ? 5.25 v v ih input high voltage 2.4 ? v cc v v il input low voltage gnd ? 0.4 v t op operating temperature -40 ? +85 c commercial symbol characteristics min. typ. max. units i cc (1) supply current @ 2.048 mb/s ? 16 25 m a @ 4.096 mb/s ? 26 40 m a @ 8.192 mb/s ? 50 75 m a v ih input high voltage 2.0 ?? v v ol input low voltage ?? 0.8 v i il (2) input leakage (input pins) ?? 15 a i bl input leakage (i/o pins) ?? 50 a c i input pin capacitance ?? 10 pf i oz high-impedance leakage ?? 5 a v oh output high voltage 2.4 ?? v v ol output low voltage ?? 0.4 v c o output pin capacitance ?? 10 pf figure 6. output load s1 is open circuit except when testing output levels or high impedance states. s2 is switched to v cc or gnd when testing output levels or high impedance states. symbol parameter min. max. unit v cc supply voltage 6.0 v vi voltage on digital inputs gnd -0.3 v cc +0.3 v i o current at digital outputs 20 ma t s storage temperature -65 +125 c p d package power dissapation ? 2w note: 1. exceeding these values may cause permanent damage. functional operation under these conditions is not implied. 2
"
20 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 $ 1
note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . symbol characteristics min. typ. max. units t fpw frame pulse width (st-bus ? , gci) ? bit rate = 2.048 mb/s 26 ? 295 ns bit rate = 4.096 mb/s 26 ? 145 ns bit rate = 8.192 mb/s 26 ? 80 ns t fps frame pulse setup time before clk falling (st-bus ? or gci) 10 ?? ns t fph frame pulse hold time from clk falling (st-bus ? or gci) 16 ?? ns t cp clk period ? bit rate = 2.048 mb/s 190 ? 300 ns bit rate = 4.096 mb/s 110 ? 150 ns bit rate = 8.192 mb/s 55 ? 70 ns t ch clk pulse width high ? bit rate = 2.048 mb/s 85 ? 150 ns bit rate = 4.096 mb/s 50 ? 75 ns bit rate = 8.192 mb/s 20 40 ns t cl clk pulse width low ? bit rate = 2.048 mb/s 85 ? 150 ns bit rate = 4.096 mb/s 50 ? 75 ns bit rate = 8.192 mb/s 20 ? 40 ns t r , t f clock rise/fall time ?? 10 ns t hfpw wide frame pulse width ? bit rate = 8.192 mb/s 195 ? 295 ns t hfps frame pulse setup time before hclk falling 10 ? 150 ns t hfph frame pulse hold time from hclk falling 20 ? 150 ns t hcp hclk (4.096 mhz) period ? bit rate = 8.192 mb/s 190 ? 300 ns t hch hclk (4.096 mhz) pulse width high ? bit rate = 8.192 mb/s 85 ? 150 ns t hcl hclk (4.096 mhz) pulse width low ? bit rate = 8.192 mb/s 85 ? 150 ns t hr , t hf hclk rise/fall time ?? 10 ns t dif delay between falling edge of hclk and falling edge of clk -10 ? 10 ns symbol characteristics min. typ. max. unit test conditions t sis rx setup time 0 ?? ns t sih rx hold time 20 ?? ns t sod tx delay ? active to active ?? 39 ns c l = 30pf ?? 58 ns c l = 200pf t dz tx delay ? active to high-z ?? 37 ns r l = 1k ? , c l = 200pf t zd tx delay ? high-z to active ?? 37 ns r l = 1k ? , c l = 200pf t ode output driver enable (ode) delay ?? 37 ns r l = 1k ? , c l = 200pf t xcd cco output delay ?? 48 ns c l = 30pf ?? 58 ns c l = 200pf $ 1 "
21 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 bit 1, channel 0 bit 0, channel 0 bit 7, last ch (1) bit 2, channel 0 bit 1, channel 0 bit 0, channel 0 bit 7, last ch (1) bit 2, channel 0 t fpw t fph t ch t cl t f t r t fps t sod t sis t sih f0i clk tx rx t cp 5713 drw11 note : 1. 2.048 mb/s mode, last channel = ch 31, 4.096 mb/s mode, last channel = ch 63, 8.192 mb/s mode, last channel = ch 127. figure 8. gci timing at 2.048 mb/s and high speed serial interface at 4.096 mb/s or 8.192 mb/s, when wfps pin = 0 t fpw t fph t ch t cl t f t r t fps t sod t sis t sih f0i clk tx rx t cp 5713 drw10 bit 6, channel 0 bit 7, channel 0 bit 0, last ch (1) bit 5, channel 0 bit 6, channel 0 bit 7, channel 0 bit 0, last ch (1) bit 5, channel 0 note: 1. 2.048 mb/s mode, last channel = ch 31, 4.096 mb/s mode, last channel = ch 63, 8.192 mb/s mode, last channel = ch 127. figure 7. st-bus ? timing for 2.048 mb/s and high speed serial interface at 4.096 mb/s or 8.192 mb/s, when wfps pin = 0.
22 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 t xcd t zd clk (st-bus ? or wfps mode) clk (gci mode) cco 5713 drw13 tx tx valid data valid data t dz ode tx valid data 5713 drw14 t ode t ode figure 10. serial output and external control figure 11. output driver enable (ode) t hfph t dif f0i tx rx 5713 drw12 bit 1, ch 127 bit 0, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 bit 1, ch 127 bit 0, ch 127 bit 7, ch 0 bit 6, ch 0 bit 5, ch 0 bit 4, ch 0 t hfps t hfpw clk 16.384 mhz hclk 4.096 mhz t hch t hcp t cp t ch t cl t r t sod t f t sis t sih t hcl t hf t hr figure 9. wfp bus timing for high speed serial interface (8.192 mb/s), when wfps pin = 1 note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
23 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 t alw address data t ads t adh ale 5713 drw15 t rw t ww t csrw t alrd t csr t csw t dhw t dhr t akh t ddr t dsw t swd t alwr t akd ad0-ad7 d8-d15 cs rd wr dta figure 12. multiplexed bus timing (intel mode) $ 1 2

" note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l . symbol parameter min. typ. max. units test conditions t alw ale pulse width 20 ?? ns t ads address setup from ale falling 10 ?? ns t adh address hold from ale falling 10 ?? ns t alrd rd active after ale falling 10 ?? ns t ddr data setup from dta low on read 10 ?? ns c l = 150pf t csrw cs hold after rd / wr 0 ?? ns t rw rd pulse width (fast read) ? 80 ? ns t csr cs setup from rd 0 ?? ns t dhr (1) data hold after rd 10 ? 75 ns c l = 150pf, r l = 1k t ww wr pulse width (fast write) 45 ?? ns t alwr wr delay after ale falling 3 ?? ns t csw cs setup from wr 0 ?? ns t dsw data setup from wr (fast write) 20 ?? ns t swd valid data delay on write (slow write) ?? 122 ns t dhw data hold after wr inactive 5 ?? ns t akd acknowledgment delay: reading/writing registers 50/60 ns c l = 150pf reading/writing memory ? @ 2.048 mb/s 760/780 ns c l = 150pf @ 4.096 mb/s 400/420 ns c l = 150pf @ 8.192 mb/s 220/240 ns c l = 150pf t akh (1) acknowledgment hold time ? 45 80 ns c l = 150pf, r l = 1k
24 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ds 5713 drw16 address t css t dsh t asw t csh t ddr t ads t adh ad0-ad7 d8-d15 wr cs dta data address data t rws t dws t sw t dhw t akd ad0-ad7 d8-d15 rd r/ w as t rwh t dhr t akh $ 1 2
" figure 13. multiplexed bus timing (motorola mode) symbol parameter min. typ. max. units test conditions t asw ale pulse width 80 ?? ns t ads address setup from as falling 10 ?? ns t adh address hold from as falling 10 ?? ns t ddr data setup from dta low on read 10 ?? ns c l = 150pf t csh cs hold after ds falling 0 ?? ns t css cs setup from ds rising 0 ?? ns t dhw data hold after write 10 ?? ns t dws data setup from ds ? write (fast write) 25 ?? ns t swd valid data delay on write (slow write) ?? 122 ns t rws r/ w setup from ds rising 60 ?? ns t rwh r/ w hold from ds rising 10 ?? ns t dhr (1) data hold after read 10 50 75 ns c l = 150pf, r l = 1k t dsh ds delay after as falling 10 ?? ns t akd acknowledgment delay: reading/writing registers 55/60 ns c l = 150pf reading/writing memory ? @ 2.048 mb/s 760/780 ns c l = 150pf @ 4.096 mb/s 400/420 ns c l = 150pf @ 8.192 mb/s 220/240 ns c l = 150pf t akh (1) acknowledgment hold time ? 45 80 ns c l = 150pf, r l = 1k note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
25 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 ds cs valid write address a0-a7 t css t csh r/ w t rws t rwh t ads t adh valid write data ad0-ad7/ d8-d15 t dsw t dhw dta t akd t akh t css t csh t rws t rwh valid read address t ads t adh valid read data t ddr t dhr t akd t akh 5713 drw17 t swd figure 14. motorola non-multiplexed asyncronous bus timing $ 1

1 2 symbol parameter min. typ. max. units test conditions t css cs setup from ds falling 0 ?? ns t rws r/w setup from ds falling 10 ?? ns t ads address setup from ds falling 2 ?? ns t csh cs hold after ds rising 0 ?? ns t rwh r/w hold after ds rising 5 ?? ns t adh address hold after ds rising 5 ?? ns t ddr data setup from dta low on read 0 ?? ns c l = 150pf t dhr data hold on read 10 50 75 ns c l = 150pf, r l = 1k t dsw data setup on write (fast write) 20 ?? ns t swd valid data delay on write (slow write) ?? 122 ns t dhw data hold on write 8 ?? ns t akd acknowledgment delay: reading/writing registers 55/60 ns c l = 150pf reading/writing memory ? @ 2.048 mb/s 760/780 ns c l = 150pf @ 4.096 mb/s 400/420 ns c l = 150pf @ 8.192 mb/s 220/240 ns c l = 150pf t akh (1) acknowledgment hold time ? 45 80 ns c l = 150pf, r l = 1k note: 1. high impedance is measured by pulling to the appropriate rail with r l , with timing corrected to cancel time taken to discharge c l .
26 commercial temperature range idt7290820 5v time slot interchange digital switch 2,048 x 2,048 5713 drw18 ad0-ad7 d8-d15 cs dta valid write address r/ w a0-a7 ds clk gci clk st-bus ? t dss t css t csh t rws t rwh valid read address t ads t adh valid read data t dhr t ckak t akh t ddr t dspw t dss t css t csh t rws t rwh t ads t adh valid write data t dhw t ckak t akh t swd figure 15. motorola non-multiplexed syncronous bus timing
27 *to search for sales office near you, please click the sales button found on our home page or dial the 800# above and press 2. idt logo is a registered trademark of integrated device technology, inc. and the st-bus ? is a trademark of mitel corp. corporate headquarter for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 408-330-1753 santa clara, ca 95054 fax: 408-492-8674 email: fifohelp@idt.com www.idt.com* j pkg: www.idt.com/docs/psc4008.pdf pqf pkg: www.idt.com/docs/psc4028.pdf pf pkg: www.idt.com/docs/psc4036.pdf bc pkg: www.idt.com/docs/psc4084.pdf 5713 drw19 xxxxxx idt device type x package process/ temperature range xx blank commercial (-40 c to +85 c) 7290820 2,048 x 2,048 ? time slot interchange digital switch j bc pqf pf plastic leaded chip carrier (plcc, j84-1) ball grid array (bga, bc100-1) plastic quad flatpack (pqfp, pq100-2) thin quad flat pack (tqfp, pn100-1)

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$ 5/23/2000 pgs.1, 3, 18 and 25. 8/15/2000 pgs.1, 2, 3, 6, 13 and 25. 9/22/2000 pgs. 3 and 13. 12/22/2000 pgs. 7, 12, 18, 21, 22, 23, 24 and 25. 01/24/2001 pg. 1, 16 and 18. 07/09/2001 pgs. 4, 5, 12 and 25.

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